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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . s y n c h r o n o u s b u c k p w m a n d l i n e a r c o n t r o l l e r p r o v i d e d t w o r e g u l a t e d v o l t a g e s - s y n c h r o n o u s b u c k c o n v e r t e r - l i n e a r r e g u l a t o r s i n g l e 1 2 v p o w e r s u p p l y r e q u i r e d e x c e l l e n t b o t h o u t p u t v o l t a g e r e g u l a t i o n - 0 . 8 v i n t e r n a l r e f e r e n c e - 1% over l i n e v o l t a g e a n d t e m p e r a t u r e i n t e g r a t e d s o f t - s t a r t f o r p w m a n d l i n e a r o u t p u t s p r o g r a m m a b l e f r e q u e n c y r a n g e f r o m 1 5 0 k h z t o 1 0 0 0 k h z v o l t a g e m o d e p w m c o n t r o l d e s i g n a n d u p t o 8 9 % ( t y p . ) d u t y c y c l e u n d e r - v o l t a g e p r o t e c t i o n f o r p w m a n d l i n e a r o u t p u t o v e r - c u r r e n t p r o t e c t i o n f o r p w m o u t p u t - s e n s e l o w - s i d e m o s f e t ? s r d s ( o n ) s o p - 1 4 , q s o p - 1 6 a n d q f n 4 x 4 - 1 6 p a c k a g e s l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) the apw7067n integrates synchronous buck pwm and linear controller, as well as monitoring and protection functions into a single package. the synchronous pwm controller drives dual n-channel mosfets, which provides one controlled power output with under-voltage and over- current protections. linear controller drives an external n-channel mosfet with under-voltage protection. the apw7067n provides excellent regulation for output load variation. an internal 0.8v temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. the switching frequency is adjustable from 150khz to 1000khz. the apw7067n with excellent protection functions: por, ocp and uvp. the power-on-reset (por) circuit can monitor vcc12 supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides both outputs with controlled rising voltage. the over-current protection (ocp) monitors the output current by using the voltage drop across the lower mosfet?s r ds(on) , comparing with internal v ocp (0.25v), eliminating the need for a current sensing resister. when the output current reaches the trip point, the controller will shutdown the ic directly, and latch the converter?s output. the under-voltage protection (uvp) monitors the voltages of fb and fbl pins for short- circuit protection. when the v fb or v fbl is less than 50% of v ref , the controller will shutdown the ic directly. g r a p h i c c a r d s f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s t y p i c a l a p p l i c a t i o n c i r c u i t v out1 v in1 l q1 pwm controller q2 linear controller v out2 q3 v in2 12v r fs_dis
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n p i n c o n f i g u r a t i o n symbol parameter rating unit v cc12 vcc 12 to gnd - 0.3 to +16 v v boot boot to phase - 0.3 to +16 v v ugate ugate to phase <400ns pulse width >400ns pulse width - 5 to v boot +5 - 0.3 to v boot +0.3 v v lgate lgate to p gnd <400ns pulse width >400ns pulse width - 5 to v cc12 +5 - 0.3 to v cc12 +0.3 v v phase phase to gnd < 2 00ns pulse width > 2 00ns pulse width - 10 to + 30 - 0.3 to 16 v a b s o l u t e m a x i m u m r a t i n g s (note 1) n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 c f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . 1 3 2 4 6 5 7 boot fs_dis drive fb comp gnd fbl 14 12 13 11 9 10 8 ugate phase nc lgate pgnd vcc12 nc sop-14 top view 1 3 2 4 6 5 7 8 boot fs_dis drive fb comp gnd fbl gnd 16 14 15 13 11 12 10 9 ugate phase nc lgate pgnd vcc12 nc vcc12 qsop-16 top view 1 3 2 4 6 5 7 8 b o o t f s _ d i s drive fb comp a g n d fbl d g n d u g a t e p h a s e nc lgate pgnd v c c 1 2 nc v c c 1 2 qfn4x4-16 top view 12 10 11 9 15 16 14 13 metal gnd pad (bottom) apw7067n handling code temp. range package code apw7067n k : apw7067n xxxxx xxxxx - date code assembly material apw7067n qa : xxxxx - date code apw7067n m : xxxxx - date code apw7067n xxxxx apw7067n xxxxx package code k : sop - 14 m : qsop - 16 qa : qfn4x4 - 16 temp. range e : -20 to 70 c handling code tr : tape & reel assembly material l : lead free device g : halogen and lead free device
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 3 symbol parameter rating unit v cc12 ic supply voltage 10.8 to 13.2 v v in1 converter input voltage 2. 9 to 13.2 v v out1 converter output voltage 0. 9 to 5 v i out1 converter output current 0 to 30 a i out2 linear output current 0 to 3 a t a ambient tempera ture range - 20 to 70 c t j junction temperature range - 2 0 to 125 c symbol parameter rating unit v drive drive to gnd 12 v v fb, v fbl, v comp, v fs_dis fb, fbl, comp, fs_dis to gnd - 0.3 to 7 v v pgnd pgnd to gnd - 0.3 to +0.3 v t j junction temperature range - 2 0 to +150 c t stg storage temperature - 65 ~ 150 c t sdr maximum lead soldering temperature, 10 seconds 260 c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s n o t e 4 : r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t s e l e c t r i c a l c h a r a c t e r i s t i c s a b s o l u t e m a x i m u m r a t i n g s ( c o n t . ) n o t e 1 : a b s o l u t e m a x i m u m r a t i n g s a r e t h o s e v a l u e s b e y o n d w h i c h t h e l i f e o f a d e v i c e m a y b e i m p a i r e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c 1 2 = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . apw7067n symbol parameter test conditions min typ max unit input supply current vcc12 supply current (shutdown mode) ugate, lgate and drive open; fs_dis = gnd 4 6 ma i cc12 vcc12 supply current ugate, lgate and drive open ; f osc = 6 0 0khz 1 6 24 m a power - on reset rising vcc12 threshold 7.7 7.9 8.1 v falling vcc12 threshold 7.2 7.4 7.6 v oscillator accuracy - 15 +15 % f osc oscillator frequency r fs_dis = 11 0k ohms 255 30 0 345 khz f osc oscillator frequency r fs_dis = 47 k ohms 510 6 0 0 690 k hz v osc ramp amplitude (nominal 1.2v to 2.7v) (note 2) 1 .5 v duty maximum duty cycle 89 % reference v ref reference voltage for error amp1 and amp2 0.792 0.80 0.808 v reference voltage tolerance - 1 +1 % pwm load regulation i out 1 = 0 to 10a 1 % linear load regulation i out 2 = 0 to 3a 1 %
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c 1 2 = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . apw7067n symbol parameter test conditions min typ max unit pwm e rr or amplifier gain open loop gain r l = 10k, c l = 10p f (note 2) 93 db gbwp open loop bandwidth r l = 10k, c l = 10p f (note 2) 20 mhz sr slew rate r l = 10k, c l = 10p f (note 2) 8 v/ m s fb input current v fb = 0.8v 0.1 1 m a v co mp comp high voltage 5 v v co mp comp low voltage 0 v i comp comp source current v co mp = 2v 12 ma i comp comp sink current v co mp = 2v 12 ma gate drivers i ugate upper gate source current 2.5 a i ugate upper gate s ink current v boot = 12 v, v ugate - v phase = 2 v 2 a i lgate low er gate source current 2.5 a i lgate low er gate s ink current v cc12 = 12 v, v lgate = 2 v 3.5 a r ugate upper gate s ource impedance v boot = 12v, i ugate = 0. 1 a 2.25 3.375 w r ugate upper gate sink impedance v boot = 12v, i ugate = 0. 1 a 0.7 1.05 w r l gate lower gate source impedance v cc12 = 12v, i l gate = 0. 1 a 2.25 3.375 w r lgate lower gate sink impedance v cc12 = 12v, i l gate = 0. 1 a 0.4 0.6 w t d dead time 20 ns linear regu lator gain open loop gain r l = 10k, c l = 10p f (note 2) 70 db gbwp open loop bandwidth r l = 10k, c l = 10p f (note 2) 19 mhz sr slew rate r l = 10k, c l = 10p f (note 2) 6 v/ m s fbl input current v fbl = 0.8 v 0.1 1 m a v drive drive high voltage 10 v v drive drive low voltage 0 v i drive drive source current v drive = 5v 4 ma i drive drive sink current v drive = 5v 3 ma protection v fb - uv fb under voltage protection trip point percent of v ref 50 % v fbl - uv fbl under voltage protection trip p oint percent of v ref 50 % v ocp ocp voltage 230 2 50 270 m v soft start f osc = 600khz 2.1 m s t ss internal soft - star t interval (note 3) f osc = 300khz 4.2 m s n o t e 2 : g u a r a n t e e d b y d e s i g n .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ugate source current (a) u g a t e v o l t a g e ( v ) u g a t e s o u r c e c u r r e n t v s . u g a t e v o l t a g e ugate sink current (a) u g a t e v o l t a g e ( v ) u g a t e s i n k c u r r e n t v s . u g a t e v o l t a g e lgate source current (a) l g a t e v o l t a g e ( v ) l g a t e s o u r c e c u r r e n t v s . l g a t e v o l t a g e lgate sink current (a) l g a t e v o l t a g e ( v ) l g a t e s i n k c u r r e n t v s . l g a t e v o l t a g e reference voltage(v) j u n c t i o n t e m p e r a t u r e ( c ) v r e f v s . j u n c t i o n t e m p e r a t u r e 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 0 1 2 3 4 5 6 7 0 1 2 3 4 v boot =12v v phase =0v v boot =12v v phase =0v v cc12 =12v v cc12 =12v 0.8005 0.801 0.8015 0.802 0.8025 0.803 0.8035 0.804 -40 -20 0 20 40 60 80 100 120 v ref
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s p o w e r o n p o w e r o f f 1 1 2 2 1 1 2 2 3 3 3 3 e n s h u t d o w n 1 1 2 2 1 1 2 2 c h 1 : v f s _ d i s ( 1 v / d i v ) c h 2 : v d r i v e ( 5 v / d i v ) c h 3 : v o u t 1 ( 1 v / d i v ) c h 4 : v o u t 2 ( 2 v / d i v ) t i m e : 5 m s / d i v 3 3 3 3 c h 1 : v c c 1 2 ( 1 0 v / d i v ) c h 2 : v o u t 1 ( 1 v / d i v ) c h 3 : v o u t 2 ( 2 v / d i v ) t i m e : 5 m s / d i v c h 1 : v f s _ d i s ( 1 v / d i v ) c h 2 : v d r i v e ( 5 v / d i v ) c h 3 : v o u t 1 ( 1 v / d i v ) c h 4 : v o u t 2 ( 2 v / d i v ) t i m e : 5 m s / d i v c h 1 : v c c 1 2 ( 1 0 v / d i v ) c h 2 : v o u t 1 ( 1 v / d i v ) c h 3 : v o u t 2 ( 2 v / d i v ) t i m e : 5 m s / d i v 4 4 4 4 v cc12 =12v, v in1 =12v,v in2 =3.3v v out1 =1.2v,v out2 =2.5v l=1uh v cc12 =12v, v in1 =12v,v in2 =3.3v v out1 =1.2v,v out2 =2.5v l=1uh v cc12 =12v, l=1uh, v in1 =12v, v in2 =3.3v v out1 =1.2v, v out2 =2.5v v cc12 =12v, l=1uh, v in1 =12v, v in2 =3.3v v out1 =1.2v, v out2 =2.5v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s ( c o n t . ) u g a t e r i s i n g u g a t e f a l l i n g 1 1 2 2 1 1 2 2 3 3 3 3 u v p _ p w m c o n t r o l l e r ( v f b < 0 . 4 v ) u v p _ l i n e a r r e g u l a t o r ( v f b l < 0 . 4 v ) 1 1 2 2 1 1 2 2 3 3 3 3 4 4 c h 1 : v u g a t e ( 2 0 v / d i v ) c h 2 : v p h a s e ( 1 0 v / d i v ) c h 3 : v l g a t e ( 1 0 v / d i v ) t i m e : 5 0 n s / d i v c h 1 : v f b ( 1 v / d i v ) c h 2 : v o u t 1 ( 1 v / d i v ) c h 3 : v u g a t e ( 2 0 v / d i v ) c h 4 : v c o m p ( 5 v / d i v ) t i m e : 5 0 m s / d i v c h 1 : v u g a t e ( 2 0 v / d i v ) c h 2 : v p h a s e ( 1 0 v / d i v ) c h 3 : v l g a t e ( 1 0 v / d i v ) t i m e : 5 0 n s / d i v c h 1 : v f b l ( 1 v / d i v ) c h 2 : v d r i v e ( 5 v / d i v ) c h 3 : v o u t 2 ( 2 v / d i v ) t i m e : 1 0 0 m s / d i v v cc12 =12v, v in1 =12v v out1 =1.2v v cc12 =12v, v in1 =12v v out1 =1.2v v cc12 =12v, v in1 =12v v out1 =1.2v, l=1uh, i out1 =10a v cc12 =12v, v in2 =12v v out2 =1.2v, i out2 =10a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 8 c h 1 : v o u t 1 ( 1 0 0 m v / d i v , a c ) c h 2 : v u g a t e ( 2 0 v / d i v ) c h 3 : i o u t 1 ( 1 0 a / d i v ) t i m e : 2 0 m s / d i v c h 1 : v o u t 1 ( 1 0 0 m v / d i v , a c ) c h 2 : v u g a t e ( 2 0 v / d i v ) c h 3 : i o u t 1 ( 1 0 a / d i v ) t i m e : 5 0 m s / d i v c h 1 : v o u t 1 ( 1 0 0 m v / d i v , a c ) c h 2 : v u g a t e ( 2 0 v / d i v ) c h 3 : i o u t 1 ( 1 0 a / d i v ) t i m e : 2 0 m s / d i v i o u t 1 = 0 a 1 0 a i o u t 1 = 0 a 1 0 a 0 a i o u t 1 = 1 0 a 0 a l o a d t r a n s i e n t r e s p o n s e ( p w m c o n t r o l l e r ) - v c c 1 2 = 1 2 v , v i n 1 = 1 2 v , v o u t 1 = 2 v , f o s c = 3 0 0 k h z - i o u t 1 s l e w r a t e = 1 0 a / m s c h 1 : v o u t 2 ( 1 0 0 m v / d i v , a c ) c h 2 : i o u t 2 ( 2 a / d i v ) t i m e : 1 m s / d i v c h 1 : v o u t 2 ( 1 0 0 m v / d i v , a c ) c h 2 : i o u t 2 ( 2 a / d i v ) t i m e : 1 0 m s / d i v c h 1 : v o u t 2 ( 1 0 0 m v / d i v , a c ) c h 2 : i o u t 2 ( 2 a / d i v ) t i m e : 1 m s / d i v i o u t 2 = 0 a 3 a i o u t 2 = 0 a 3 a 0 a i o u t 2 = 3 a 0 a l o a d t r a n s i e n t r e s p o n s e ( l i n e a r r e g u l a t o r ) - v c c 1 2 = 1 2 v , v i n 2 = 3 . 3 v , v o u t 2 = 2 . 5 v - i o u t 2 s l e w r a t e = 3 a / m s 1 1 2 2 3 3 1 1 2 2 3 3 1 1 2 2 3 3 1 1 2 2 1 1 2 2 1 1 2 2 o p e r a t i n g w a v e f o r m s ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s ( c o n t . ) o v e r c u r r e n t p r o t e c t i o n s h o r t t e s t a f t e r p o w e r r e a d y 1 1 2 2 1 1 2 2 3 3 3 3 s h o r t t e s t b e f o r e p o w e r o n 1 1 2 2 3 3 4 4 c h 1 : v o u t 1 ( 1 v / d i v ) c h 2 : v d r i v e ( 5 v / d i v ) c h 3 : v u g a t e ( 2 0 v / d i v ) c h 4 : i l ( 1 0 a / d i v ) t i m e : 5 0 m s / d i v c h 1 : v c c 1 2 ( 1 0 v / d i v ) c h 2 : v o u t 1 ( 1 v / d i v ) c h 3 : v u g a t e ( 2 0 v / d i v ) c h 4 : i l ( 1 0 a / d i v ) t i m e : 2 m s / d i v 4 4 4 4 c h 1 : v o u t 1 ( 1 v / d i v ) c h 2 : v d r i v e ( 5 v / d i v ) c h 3 : v u g a t e ( 2 0 v / d i v ) c h 4 : i l ( 1 0 a / d i v ) t i m e : 5 0 m s / d i v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 0 f u n c t i o n p i n d e s c r i p t i o n v c c 1 2 p o w e r s u p p l y i n p u t p i n . c o n n e c t a n o m i n a l 1 2 v p o w e r s u p p l y t o t h i s p i n . t h e p o w e r - o n r e s e t f u n c t i o n m o n i t o r s t h e i n p u t v o l t a g e a t t h i s p i n . i t i s r e c o m m e n d e d t h a t a d e c o u p l i n g c a p a c i t o r ( 1 t o 1 0 m f ) b e c o n n e c t e d t o g n d f o r n o i s e d e c o u p l i n g . b o o t t h i s p i n p r o v i d e s t h e b o o t s t r a p v o l t a g e t o t h e u p p e r g a t e d r i v e r f o r d r i v i n g t h e n - c h a n n e l m o s f e t . a n e x t e r n a l c a - p a c i t o r f r o m p h a s e t o b o o t , a n i n t e r n a l d i o d e , a n d t h e p o w e r s u p p l y v a l t a g e v c c 1 2 , g e n e r a t e s t h e b o o t s t r a p v o l t - a g e f o r t h e u p p e r g a t e d i v e r ( u g a t e ) . p h a s e t h i s p i n i s t h e r e t u r n p a t h f o r t h e u p p e r g a t e d r i v e r . c o n - n e c t t h i s p i n t o t h e u p p e r m o s f e t s o u r c e , a n d c o n n e c t a c a p a c i t o r t o b o o t f o r t h e b o o t s t r a p v o l t a g e . t h i s p i n i s a l s o u s e d t o m o n i t o r t h e v o l t a g e d r o p a c r o s s t h e l o w e r m o s f e t f o r o v e r - c u r r e n t p r o t e c t i o n . g n d t h i s p i n i s t h e s i g n a l g r o u n d p i n . c o n n e c t t h e g n d p i n t o a g o o d g r o u n d p l a n e . p g n d t h i s p i n i s t h e p o w e r g r o u n d p i n f o r t h e l o w e r g a t e d r i v e r . i t s h o u l d b e t i e d t o g n d p i n o n t h e b o a r d . c o m p t h i s p i n i s t h e o u t p u t o f p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e c o m p e n s a t i o n c o m p o n e n t s . f b t h i s p i n i s t h e i n v e r t i n g i n p u t o f t h e p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e o u t p u t v o l t a g e a n d t h e c o m p e n s a t i o n c o m p o n e n t s . t h i s p i n i s a l s o m o n i t o r e d f o r u n d e r - v o l t a g e p r o t e c t i o n , w h e n t h e f b v o l t a g e i s u n d e r 5 0 % o f r e f e r e n c e v o l t a g e ( 0 . 4 v ) , b o t h o u t p u t s w i l l b e s h u t - d o w n e d i m m e d i a t e l y . u g a t e t h i s p i n i s t h e g a t e d r i v e r f o r t h e u p p e r m o s f e t o f p w m o u t p u t . l g a t e t h i s p i n i s t h e g a t e d r i v e r f o r t h e l o w e r m o s f e t o f p w m o u t p u t . d r i v e t h i s p i n d r i v e s t h e g a t e o f a n e x t e r n a l n - c h a n n e l m o s f e t f o r l i n e a r r e g u l a t o r . i t i s a l s o u s e d t o s e t t h e c o m p e n s a - t i o n f o r s o m e s p e c i f i c a p p l i c a t i o n s , f o r e x a m p l e , w i t h l o w v a l u e s o f o u t p u t c a p a c i t a n c e a n d e s r . f b l t h i s p i n i s t h e i n v e r t i n g i n p u t o f t h e l i n e a r r e g u l a t o r e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e o u t p u t v o l t a g e . t h i s p i n i s a l s o m o n i t o r e d f o r u n d e r - v o l t a g e p r o t e c t i o n , w h e n t h e f b l v o l t a g e i s u n d e r 5 0 % o f r e f e r e n c e v o l t a g e ( 0 . 4 v ) , b o t h o u t p u t s w i l l b e s h u t d o w n i m m e d i a t e l y . f s _ d i s t h i s p i n b e a l l o w e d t o a d j u s t t h e s w i t c h i n g f r e q u e n c y . c o n n e c t a r e s i s t o r f r o m f s _ d i s p i n t o t h e g r o u n d t o i n c r e a s e t h e s w i t c h i n g f r e q u e n c y . t h i s p i n a l s o p r o v i d e s s h u t d o w n f u n c t i o n , u s e a n o p e n d r a i n l o g i c s i g n a l t o p u l l t h i s p i n l o w t o d i s a b l e b o t h o u t p u t s , l e a v e o p e n t o e n a b l e b o t h o u t p u t s .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 1 b l o c k d i a g r a m t y p i c a l a p p l i c a t i o n c i r c u i t s 1 3 2 4 6 5 7 boot fs_dis drive fb comp gnd fbl 14 12 13 11 9 10 8 ugate phase nc lgate pgnd vcc12 v out1 v in1 12v v out2 v in2 v out1 on/off c1 c2 r2 r1 r3 c3 r4 r5 r gnd1 r gnd2 c5 l c out1 c out2 q1 q2 c in1 c in2 r fs_dis c 6 r 6 c 4 c 7 apw7067n q3 nc apm2509 apm2506 1uh 12v 470ufx2 470ufx2 0.1uf r 7 2.2 w 1uf 2.2 w 2.2nf 22nf 1.5k 22 w 3k 3.9k 0.01uf 2.2nf 1.2v 470uf 470uf 3.3v 2.5k 1.17k 2.5v apm3055 2n7002 q4 * c5, r5 for specific application gate control soft start and fault logic power-on- reset phase lgate fb vcc12 ugate v ref 50%v ref o.c.p comparator error amp 1 pwm comparator u.v.p comparator : 2 comp boot v ref 50%v ref : 2 fbl drive oscillator fs_dis gnd u.v.p comparator v ocp 0.25v pgnd regulator v ref (0.8v) 10v 10 v error amp 2 sawtooth wave sense low side
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 2 f u n c t i o n d e s c r i p t i o n power-on-reset (por) the power-on-reset (por) function of apw7067n continually monitors the input supply voltage (v cc12 ), ensures the supply voltage exceed its rising por threshold voltage. the por function initiates soft-start interval operation while vcc12 voltage exceeds its por threshold and i nhibits operation under disabled status. s o f t - s t a r t f i g u r e 1 . s h o w s t h e s o f t - s t a r t i n t e r v a l . w h e n v c c 1 2 r e a c h e s t h e r i s i n g p o r t h r e s h o l d v o l t a g e , t h e i n t e r n a l r e f e r e n c e v o l t a g e i s c o n t r o l l e d t o f o l l o w a v o l t a g e p r o p o r t i o n a l t o t h e s o f t - s t a r t v o l t a g e . t h e s o f t - s t a r t i n t e r v a l i s v a r i a b l e b y t h e o s c i l l a t o r f r e q u e n c y . t h e f o r m u l a t i o n i s g i v e n b y : f i g u r e 2 . s h o w s m o r e d e t a i l o f t h e f b a n d f b l v o l t a g e r a m p s . t h e f b a n d f b l v o l t a g e s o f t - s t a r t r a m p s a r e f o r m e d w i t h m a n y s m a l l s t e p s o f v o l t a g e . t h e v o l t a g e o f o n e s t e p i s a b o u t 2 0 m v i n v f b a n d v f b l , a n d t h e p e r i o d o f o n e s t e p i s a b o u t 3 2 / f o s c . t h i s m e t h o d p r o v i d e s a c o n t r o l l e d v o l t a g e r i s e a n d p r e v e n t s t h e l a r g e p e a k c u r r e n t t o c h a r g e t h e o u t p u t c a p a c i t o r s . t h e f b v o l t a g e c o m p a r e s t h e f b l v o l t a g e t o s h i f t t o a n e a r l i e r t i m e t h e e s t a b l i s h m e n t a s f i g u r e 2 . t h e v o l t a g e e s t a b i l i s h m e n t t i m e d i f f e r e n c e f o r v f b a n d v f b l i s v a r i a b l e b y t h e o s c i l l a t o r . t h e f o r m u l a t i o n i s g i v e n b y : over-current protection the over-current protection monitors the output current by using the voltage drop across the lower mosfet?s r ds(on) and this voltage drop will be compared with the internal 0.25v reference voltage. when the voltage drop across the lower mosfet?s r ds(on) is larger than 0.25v, an over-current condition is detected, the controller will shutdown the ic directly, and latch the converter's output. the threshold of the over current limit is given by: f i g u r e 2 . t h e c o n t r o l l e d s t e p p e d f b a n d f b l v o l t a g e d u r i n g s o f t - s t a r t f i g u r e 1 . s o f t - s t a r t i n t e r v a l 1280 f 1 ) t t ( t osc 1 2 ss = - d = ss osc 3 4 t 4 1 320 f 1 ) t t ( = = - d voltage (v) time v cc12 v out1 t 0 por v out2 t 1 t 2 ( ) side _ low r (0.25v) v i ds(on) ocp limit = voltage(v) 20mv 20mv 32/f osc 32/f osc t 3 t 4 time v fb v fbl for the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. - the mosfet?s r ds(on) is varied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacture?s datasheet. - the minimum v ocp should be used in the above equation. - note that the i limit is the current flow through the lower mosfet; i limit must be greater than maximum output current add the half of inductor ripple current. under voltage protection the fb and fbl pin are monitored during converter op- eration by their own under voltage (uv) comparator. if the fb or fbl voltage drop below 50% of the refer- ence voltage (50% of 0.8v = 0.4v), a fault signal is inter- nally generated, and the device turns off both high-side
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 3 figure 3. oscillator frequency vs. r fs-dis f u n c t i o n d e s c r i p t i o n ( c o n t . ) under voltage protection (cont.) and low-side mosfet and the converter?s output is latched to be floating. shutdown and enable pulling the fs_dis voltage to gnd by an open drain transistor, shown in typical application circuit, shutdown the apw7067n pwm controller. in shutdown mode, the ugate and lgate turn off and pull to phase and gnd respectively. switching frequency the apw7067n provides the adjustable oscillator switching frequency . the switching frequency is determined by the value of r fs_dis (from fs_dis pin to gnd), the adjustable range from150khz to 1000khz . figure 3. shows how to select the resistor for the desired frequency. if the ic is operated in higher frequencies (ex. 600 khz or above), the slope of the curve is steep, and a small change in resistance will have a big effect on the frequency. at lower frequencies, the slope of the curve is much less steep, even a large change in resistor value doesn?t change the frequency too much. figure 4. shows more detail for the higher frequency and figure5. shows the lower frequency. f osc (khz) r ( k w ) 0 200 400 600 800 1000 1200 1400 1600 0 100 200 300 400 500 600 700 800 figure 4. oscillator frequency vs. r fs-dis (high frequency) f osc (khz) r ( k w ) figure 5. oscillator frequency vs. r fs-dis (low frequency) f osc (khz) r ( k w ) 400 600 800 1000 1200 0 10 20 30 40 50 60 70 80 100 150 200 250 300 350 400 450 500 50 150 250 350 450 550 650 750
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 4 a p p l i c a t i o n i n f o r m a t i o n output voltage selection the output voltage of pwm converter can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier , and the reference voltage is 0.8v . the output voltage is determined by: where r1 is the resistor connected from v out1 to fb and r gnd1 is the resistor connected from fb to gnd. the linear regulator output voltage v out2 is also set by means of an external resistor divider. the fbl pin is the inverter input of the error amplifier, and the reference voltage is 0.8v. the output voltage is determined by: ? ? ? ? ? + = gnd1 out1 r r1 1 0.8 v ? ? ? ? ? + = gnd2 out2 r r4 1 0.8 v where r4 is the resistor connected from v out2 to fbl and r gnd2 is the resistor connected from fbl to gnd. linear regulator input/output capacitor selection the input capacitor is chosen based on its voltage rating. under load transient condition, the input capacitor will momentarily supply the required transient current. the output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. in addition, the capacitor is chosen based on its voltage rating. linear regulator input/output mosfet selection the maximum drive voltage is about 10v when v cc12 is equal 12v. since this pin drives an external n-channel mosfet, therefore the maximum output voltage of the linear regulator is dependent upon the v gs . v out2max = 10 - v gs another criterion is its efficiency of heat removal. the power dissipated by the mosfet is given by: p d = i out2 x (v in2 ? v out2 ) where i out2 is the maximum load current, v out2 is the nominal output voltage. in some applications, heatsink might be required to help maintain the junction temperature of the mosfet below its maximum rating. linear regulator compensation selection the linear regulator is stable over all loads current. however, the transient response can be further enhanced by connecting a rc network between the fbl and drive pin. depending on the output capacitance and load current of the application, the value of this rc network is then varied. pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes with -40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network among comp, fb and v out1 should be added. the compensation network is shown in fig. 9. the output lc filter consists of the output inductor and output capacitors. the transfer function of the lc filter is given by: the poles and zero of this transfer functions are: 1 c esr s c l s c esr s 1 gain out1 out1 2 out1 lc + + + = out1 lc c l 2 1 f p = out1 esr c esr 2 1 f p = the f lc is the double poles of the lc filter, and f esr is the zero introduced by the esr of the output capacitor. figure 6. the output lc filter v phase l v out1 c out1 esr
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 5 figure 7. the lc filter gain and frequency a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) pwm compensation (cont.) f lc f esr -40db/dec -20db/dec frequency(hz) g a i n ( d b ) the pwm modulator is shown in figure 8. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modulator is given by: figure 8. the pwm modulator the compensation network is shown in figure 9. it provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by: osc in pwm v v gain d = output of error amplifier g v osc pwm comparator driver driver phase v in1 osc the poles and zeros of the transfer function are: figure 9. compensation network the closed loop gain of the converter can be written as: gain lc x gain pwm x gain amp figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1. choose a value for r1, usually between 1k and 5k. 2. select the desired zero crossover frequency f o : (1/5 ~ 1/10) x f s >f o >f esr use the following equation to calculate r2: ? ? ? ? + ? ? ? ? + = = sc3 1 r3 r1// sc2 1 r2 // sc1 1 v v gain out1 comp amp ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + = c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1 c2 r2 2 1 f z1 p = ( ) c3 r3 r1 2 1 f z2 + p = ? ? ? ? + p = c2 c1 c2 c1 r2 2 1 f p1 c3 r3 2 1 f p2 p = v ref v out1 v comp r 1 r 3 c 3 r 2 c 2 c 1 fb 3. place the first zero f z1 before the output lc filter double pole frequency f lc . f z1 = 0.75 x f lc calculate the c2 by the equation: r1 f f v v r2 lc o in osc d = 4. set the pole at the esr zero frequency f esr : f p1 = f esr calculate the c1 by the equation: 0.75 f r2 2 1 c2 lc p = 1 f c2 r2 2 c2 c1 esr - p =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 6 5. set the second pole f p2 at the half of the switching frequency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at f p2 with the capabilities of the error amplifier. f p2 = 0.5 x f s f z2 = f lc combine the two equations will get the following component calculations: a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) pwm compensation (cont.) 1 f 2 f r1 r3 lc s - = s f r3 1 c3 p = figure 10. converter gain and frequency output inductor selection the inductor value determines the inductor ripple current and affects the load transient response. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: where fs is the switching frequency of the regulator. although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor?s ripple current and the regulator load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f s ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfet and the power dissipation of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this will result in a larger out- put ripple voltage. output capacitor selection higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore, selecting high performance low esr capacitors is intended for switching regulator applications. in some applications, multiple capacitors have to be parallel to achieve the desired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rating and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out1 /2 , where i out1 is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge f lc frequency(hz) g a i n ( d b ) 20log (r2/r1) 20log (v in / g v osc ) f z1 f z2 f p1 f p2 f esr pwm & filter gain converter gain compensation gain in1 out1 s out1 in1 ripple v v l f v v i - = esr i v ripple out1 = d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) input capacitor selection (cont.) tested by the manufactures. if in doubt, consult the capacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1 m f can be connected between the drain of upper mosfet and the source of lower mosfet. mosfet selection the selection of the n-channel power mosfets are determined by the r ds(on) , reverse transfer capacitance (c rss ) and maximum output current requirement. there are two components of loss in the mosfets: conduction loss and transition loss. for the upper and lower mosfet, the losses are approximately given by the following: p upper = i out1 2 (1+ tc)(r ds(on) )d + (0.5)( i out1 )(v in1 )( t sw )f s p lower = i out1 2 (1+ tc)(r ds(on) )(1-d) where i out1 is the load current tc is the temperature dependency of r ds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction loss while the upper mosfet include an additional transition loss. the switching internal, t sw , is a function of the reverse transfer capacitance c rss . the (1+tc) term is to factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs tempera ture? curve of the power mosfet.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 8 l a y o u t c o n s i d e r a t i o n in any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. with power devices switching at 300khz or above, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. and signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. figure 11. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a checklist for your layout: - the metal plate of the bottom of the packages (qfn-16) must be soldered to the pcb and connected to the gnd plane on the backside through several thermal vias. - keep the switching nodes (ugate, lgate and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ug, lg, drive) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, the resistor dividers and boot capacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). - the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in1 and phase nodes) should be a large plane for heat sinking. figure 11. layout guidelines vcc12 boot phase ugate lgate v in1 v out1 l o a d apw7067n drive fbl l o a d v out2 v in2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 1 9 p a c k a g e i n f o r m a t i o n s o p ? 1 4 s y m b o l min. max. 1.75 0.10 0.17 0.25 0.25 a a1 c d e e1 e h l millimeters b 0.31 0.51 sop-14 0.25 0.50 0.40 1.27 min. max. inches 0.069 0.004 0.012 0.020 0.007 0.010 0.010 0.020 0.016 0.050 0 0.010 1.27 bsc 0.050 bsc a2 1.25 0.049 0 8 0 8 l view a 0 . 2 5 seating plane gauge plane note: 1. follow jedec ms-012 ab. 2. dimension ? d ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension ? e ? does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 3.80 5.80 8.55 4.00 6.20 8.75 0.337 0.344 0.228 0.244 0.150 0.157 d e b e 1 e see view a c h x 4 5 a a 1 a 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 2 0 p a c k a g e i n f o r m a t i o n 0 l view a 0 . 2 5 gauge plane seating plane a a 1 e 1 e h x 4 5 c see view a d b e a 2 s y m b o l min. max. 1.75 1.24 0.15 0.25 a a2 c d e e l h millimeters b 0.20 0.30 0.635 bsc qsop-16 0.25 0.50 0.40 1.27 0.025 bsc min. max. inches 0.069 0.049 0.008 0.012 0.006 0.010 0.010 0.020 0.016 0.050 0 0.10 a1 0.25 0.004 0.010 4.90 bsc 0.193 bsc 5.99 bsc 0.236 bsc e1 3.91 bsc 0.154 bsc 0 8 0 8 q s o p - 1 6
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 2 1 p a c k a g e i n f o r m a t i o n q f n 4 x 4 - 1 6 a d e a1 a3 pin 1 corner e 2 l d2 e b s y m b o l min. max. 1.00 0.00 0.25 0.35 2.50 2.80 0.05 2.50 a a1 b d d2 e e2 e l millimeters a3 0.20 ref qfn4*4-16 0.30 0.50 2.80 0.008 ref min. max. inches 0.039 0.000 0.010 0.014 0.098 0.110 0.098 0.012 0.020 0.80 0.110 0.031 0.002 4.00 bsc 0.157 bsc 4.00 bsc 0.157 bsc 0.65 bsc 0.026 bsc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 2 2 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 16.0 ? 0.30 1.75 ? 0.10 7.50 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 14 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0 .40 6.40 ? 0.20 9.00 ? 0.20 2.10 ? 0.20 application a h t1 c d d w e1 f 330 1 62 +1.5 12.75+ 0.15 2 0.5 12.4 0.2 2 0.2 12 0. 3 8 0.1 1.75 0.1 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 qsop - 16 5.5 1 1.55 +0.1 1.55+ 0.25 4.0 0.1 2.0 0.1 6.4 0.1 5.2 0. 1 2.1 0.1 0.3 0.013 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 qfn4x4 - 16 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.10 1.5+0.10 - 0 .00 1.5 min. 0.6+0.00 - 0.40 4.35 ? 0.20 4.35 ? 0.20 1.1 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 2 3 r e f l o w c o n d i t i o n ( i r / c o n v e c t i o n o r v p r r e f l o w ) t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 t e m p e r a t u r e time critical zone t l to t p test item method description solderability mil - std - 883d - 2003 245 c, 5 sec holt mil - std - 883d - 1005.7 1000 hrs bias @125 c pct jesd - 22 - b,a102 168 hrs, 100 % rh, 121 c tst mil - std - 883d - 1011.9 - 65 c~150 c, 200 cycles esd mil - std - 883d - 3015.7 vhbm > 2kv, vmm > 200v latch - up jesd 78 10ms, 1 tr > 100ma r e l i a b i l i t y t e s t p r o g r a m package type unit quantity sop - 14 tape & reel 2500 qsop - 16 tape & reel 2500 qfn4x4 - 16 tape & reel 3000 d e v i c e s p e r u n i t
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - m a r . , 2 0 0 8 a p w 7 0 6 7 n w w w . a n p e c . c o m . t w 2 4 c u s t o m e r s e r v i c e table 1. snpb entectic process ? package peak reflow temperature s package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 240 +0/ - 5 c 225 +0/ - 5 c 3 2.5 mm 225 +0/ - 5 c 225 +0/ - 5 c table 2. pb - free process ? package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 +0 c* 260 +0 c* 260 +0 c* 1.6 mm ? 2.5 mm 260 +0 c* 250 +0 c* 245 +0 c* 3 2.5 mm 250 +0 c* 245 +0 c* 245 +0 c* * tolerance: the device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 c. for example 260 c+0 c) at the rated msl level. a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat - temperature min (tsmin) - temperature max (tsmax) - time (min to max) (ts) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 180 seconds time maintained above: - temperature (t l ) - time (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak /classificatioon temperature (tp) see table 1 see table 2 time within 5 c of actual peak temperature (tp) 10 - 30 seconds 20 - 40 seconds ramp - down rate 6 c/se cond max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. notes: all temperatures refer to topside of the package. measured on the body surface.

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